(a) Field of the Invention
The present invention relates to a ferroelectric memory device having a protective layer and, more particularly, to a ferroelectric memory device having a ferroelectric capacitor and a memory cell transistor in combination in each memory cell.
(b) Description of a Related Art
A ferroelectric memory device including a ferroelectric capacitor having a ferroelectric film as a capacitor film is extensively developed for use in a variety of electronic applications. The ferroelectric capacitor stores data by using the state of polarization of the ferroelectric film sandwiched between electrodes of the ferroelectric capacitor, wherein the ferroelectric film has a remnant polarization capable of being switched in the direction thereof by an applied voltage.
FIG. 1 shows an example of a memory cell having a ferroelectric capacitor in a conventional ferroelectric memory device, and FIG. 2 shows an equivalent circuit diagram of the memory cell of FIG. 1. The memory cell 30 includes a cell transistor 24 implemented by a FET and a cell capacitor 25 implemented as a ferroelectric capacitor. The FET 24 has a pair of source/drain regions 18 including one connected to a bit line BL extending in a row direction and the other connected to a first electrode of the ferroelectric capacitor 25, and a gate connected to a word line WL extending in a column direction. The ferroelectric capacitor 25 has a second electrode connected to a plate line PL extending in the column direction. A plurality of memory cells are arranged in a matrix to form a memory cell array of a large-scale ferroelectric memory device.
FIG. 3 shows a hysteresis polarization characteristic of the ferroelectric film, with the applied voltage (volts) and the polarization (xcexccoulomb per centimeter) of the ferroelectric film being plotted on the abscissa and the ordinate, respectively. The applied voltage is plotted in a positive direction if the plate line PL is applied with a positive voltage with respect to the bit line BL. When the word line WL and the bit line BL are applied with 5 volts, for example, and the plate line PL is applied with zero volt, the ferroelectric film stays at point xe2x80x9cAxe2x80x9d of the polarization curve in FIG. 3, and then shits to point xe2x80x9cBxe2x80x9d if the bit line BL is subsequently applied with zero volt with the remaining lines being maintained at the previous voltages.
On the other hand, when the word line WL and the plate line PL are applied with 5 volts, with the bit line being applied with zero volt, the ferroelectric film stays at point xe2x80x9cCxe2x80x9d, and then shits to point xe2x80x9cDxe2x80x9d if the plate line PL is applied subsequently with zero volt. By defining xe2x80x9c1xe2x80x9d for the state of the ferroelectric film at point xe2x80x9cBxe2x80x9d, and xe2x80x9c0xe2x80x9d for the state at point xe2x80x9cDxe2x80x9d, the ferroelectric capacitor stores data after applying the described voltages.
It is desirable that the ferroelectric film have a large difference between the remnant polarizations at points xe2x80x9cDxe2x80x9d and xe2x80x9cBxe2x80x9d for improving the storage characteristic and programming. characteristic. The term xe2x80x9cstorage characteristicxe2x80x9d means reliability of the ferroelectric capacitor storing the data without an error whereas the term xe2x80x9cprogramming characteristicsxe2x80x9d means resistance or tolerance of the ferroelectric capacitor against defects due to a large number of times for overwriting of the stored data.
FIGS. 4 and 5 depict cross-sections of the memory cell of FIG. 1 taken along lines IVxe2x80x94IV and Vxe2x80x94V, respectively, in FIG. 1. The cell transistor includes source/drain regions 18 implemented by n+-diffused regions in the surface region of the semiconductor substrate 11, and a gate 17 formed on the semiconductor substrate 11 with an intervention of a gate oxide film not shown in the figure. The bit line including Al as a main component thereof is connected to one of the source/drain regions 18 of the cell transistor.
The ferroelectric capacitor 25 is disposed above the cell transistor, and includes a bottom electrode 13, a ferroelectric film 14 and a top electrode 15. The ferroelectric capacitor 25 is protected by a cover film 19 made of SiO2, for example.
An alumina (Al2O3) film may be interposed between the ferroelectric capacitor 25 and the cover film 19 for prevention of thermal evaporation of elements constituting the ferroelectric material during the fabrication process, as described in xe2x80x9cProceedings of International Symposium on Integrated Ferroelectricsxe2x80x9d, for example. The top electrode 15 is connected to the other of the source/drain regions 18 through an interconnect layer 16.
In the Configuration of the conventional ferroelectric memory device, the word line WL implements the gate electrodes 17 of the cell transistors, whereas the plate line PL implements the bottom electrodes 13 of the ferroelectric capacitors 25. The ferroelectric film 14 is made from PZT [(Pb,La)(Zr,Ti)O3] or SBT [SrBi2(Nb,Ta)2O9]
The ferroelectric film 14 is generally formed in an oxidation ambient, often followed by a thermal annealing treatment in an oxygen ambient for stabilization of the ferroelectric film 14. In view of the thermal annealing, noble metals such as Pt or Ir, or conductive oxides such as IrO2 and RuO2 having an acid resistance are generally used for the material of the top and bottom electrodes. On the other hand, a layered structure including WSi2 film, TiN film and Al film is generally used for the material of the interconnect layer 16 in view of the feasibility of fine patterning, excellent adherence with respect to Si or SiO2 and a low resistivity.
In a thermal treatment during fabrication of the ferroelectric memory device, it is known that Si diffuses into the Al film if the Al film is disposed in direct contact with Si in the diffused region. This may cause destruction of the p-n junction formed between the diffused region 18 and the semiconductor substrate 11. A TiN film is often used as a barrier film for prevention of the mutual diffusion between Al and Si, whereby the layered structure for the interconnect layer 16 includes, as mentioned above, WSi2, TiN and Al as viewed from the bottom. In this configuration, it is considered that TiN has a poor adherence with respect to Si and SiO2 and a high contact resistance with respect to Si, and that WSi2 has a function for suppressing degradation of the polarization characteristic of the ferroelectric material after formation of the interconnect layers, as described in Patent Publication JP-A-10-095846.
An interlayer dielectric film 20 such as silicon oxide film is deposited on the interconnect layer 16, followed by formation of a protective layer (insulator film) 21 such as SiNx film or SiOxNy film for prevention of water, as described in Patent Publication JP-A-4-15957. The SiNx film or SiOxNy film as used herein protects the interconnect layer having Al as a main component thereof against corrosion due to water entering from atmosphere.
FIGS. 6A to 6C show sectional views, taken along line Vxe2x80x94V in FIG. 1, of the memory cell in consecutive steps of fabrication thereof. In FIG. 6A, the ferroelectric capacitor 25 including the bottom electrode 13, the ferroelectric film 14 and the top electrode 15 is formed on an interlayer dielectric film 26, followed by formation of the cover film 19 thereon. Subsequently, via holes 27 are formed for exposing the diffused regions 18 of the substrate 11 and the top electrode 15 of the ferroelectric capacitor 25, as shown in FIG. 6B. Thereafter, the interconnect layer 16 for connecting one of the diffused regions 18 and the top electrode 15 as well as the bit line are formed. Further, the interlayer dielectric film 20 and the protective film 22 such as SiNx film or SiOxNy film are consecutively formed on the interconnect layer 16 and the bit line, as shown in FIG. 6C. The protective film 22 is formed by using a plasma-enhanced CVD (PECVD) process at a substrate temperature of about 300xc2x0 C.
The PECVD process as used for depositing the protective film 22 has a problem in that the process causes reduction of the remnant polarization of the ferroelectric film. It is considered that the reduction results from the tensile stress acting on the ferroelectric film 14 and generated by lowering the temperature of the SiNx film or SiOxNy film (referred to sometimes as simply SiNx film hereinafter) 22 after the formation thereof.
The fact that the ferroelectric film has a remnant polarization without a continued applied voltage results from the tolerance of the ferroelectric film, which is generated by the crystal strain for resisting the Coulomb force canceling the remnant polarization. Thus, the polarization characteristic of the ferroelectric film is generally affected by the stress acting on the ferroelectric film.
It can be understood that the PECVD process for the SiNx film generates a thermal stress acting as a tensile stress on the ferroelectric film, from the following description.
When the substrate temperature is raised up to 300xc2x0 C. for the PECVD process, both the interconnect layer and the ferroelectric film thermally expand. Since the interconnect layer made of a metal or alloy has a higher coefficient of thermal expansion compared to the ferroelectric film, the ferroelectric film is applied with a tensile stress by the interconnect layer at this stage. While the substrate temperature is lowered after the deposition of the SiNx film, the interconnect layer contracts. The contraction of the interconnect layer is prevented by the ferroelectric film having a lower coefficient of thermal expansion.
Therefore, after the substrate temperature is lowered to a room temperature, the thermal stress acting as the tensile stress remains on the ferroelectric film as the residual stress. The reduction of the remnant polarization is considered due to the residual tensile stress on the ferroelectric film. The reduction of the remnant. polarization degrades the storage characteristic and the programming characteristic of the ferroelectric capacitor.
In view of the above, it is an object of the present invention to provide a ferroelectric memory device having a ferroelectric capacitor in each memory cell, which has an excellent storage characteristic and an excellent programming characteristic.
It is another object of the present invention to provide a method for fabricating the ferroelectric memory device as described above.
The present invention provides a ferroelectric memory device including: an array of memory cells each having a cell transistor and a ferroelectric capacitor formed on a semiconductor substrate: a peripheral circuit: an interconnection structure for connecting the cell transistor, the ferroelectric capacitor and the peripheral circuit to store data in each of the memory cells, the ferroelectric capacitor including a bottom electrode, a ferroelectric film and a top electrode, the interconnection structure including a first interconnect layer in contact with the top electrode: an interlayer dielectric film formed on the first interconnect layer: an insulator film overlying the interlayer dielectric film and including at least one of SiNx and SiOxNy: and a protective layer disposed between the interlayer dielectric film and the insulator film and having a higher modulus of elasticity than said interconnect layer.
The protective layer preferably includes at least one of Ir, IrO2, Ru, RuO2 and Al2O3 as a main component thereof.
The present invention also provides a method for fabricating a ferroelectric memory device including the steps of: forming a cell transistor on a semiconductor substrate in each cell area: forming a ferroelectric capacitor overlying the cell transistor in the each cell area, the ferroelectric capacitor including a bottom electrode, ferroelectric film and a top electrode: forming an interconnect layer in contact with the top electrode: forming an interlayer dielectric film on the interconnect layer: forming a protective layer overlying the interlayer dielectric film, the protective layer having a higher modulus of elasticity than the interconnect layer: and forming an insulator film overlying the protective layer, the insulator film including at least one of SiNx or SiOxNy.
In accordance with the ferroelectric memory device of the present invention or manufactured by the method of the present invention, the protective layer suppresses reduction of the remnant polarization of the ferroelectric film during formation of the insulator film including SiNx or SiNOxNy to improve the storage characteristic and the programming characteristic of the ferroelectric capacitor, due to the higher modulus of elasticity of the protective layer, which prevents transferring of the stress during formation of the insulator layer.